Semiconductor processing methods frequently involve patterning layers of materials to form a transistor gate structure. FIG. 1 illustrates a semiconductive wafer fragment 10 at a preliminary step of a prior art gate structure patterning process. Semiconductive wafer fragment 10 comprises a substrate 12 having a stack 14 of materials formed thereover. Substrate 12 can comprise, for example, monocrystalline silicon lightly doped with a p-type background dopant. To aid in interpretation of the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Stack 14 comprises a gate oxide layer 16, a polysilicon layer 18, a metal silicide layer 20, an oxide layer 22, a nitride layer 24, an antireflective material layer 26, and a photoresist layer 28. Gate oxide layer 16 can comprise, for example, silicon dioxide, and forms an insulating layer between polysilicon layer 18 and substrate 12. Polysilicon layer 18 can comprise, for example, conductively doped polysilicon, and will ultimately be patterned into a first conductive portion of a transistor gate.
Silicide layer 20 comprises a metal silicide, such as, for example, tungsten silicide or titanium silicide, and will ultimately comprise a second conductive portion of a transistor gate. Prior to utilization of silicide layer 20 as a conductive portion of a transistor gate, the silicide is typically subjected to an anneal to improve crystallinity and conductivity of the silicide material of layer 20. Such anneal can comprise, for example, a temperature of from about 800° C. to about 900° C. for a time of about thirty minutes with a nitrogen (N2) purge.
If silicide layer 20 is exposed to gaseous forms of oxygen during the anneal, the silicide layer can become oxidized, which can adversely effect conductivity of the layer. Accordingly, oxide layer 22 is preferably provided over silicide layer 20 prior to the anneal. Oxide layer 22 can comprise, for example, silicon dioxide. Another purpose of having oxide layer 22 over silicide layer 20 is as an insulative layer to prevent electrical contact of silicide layer 20 with other conductive layers ultimately formed proximate silicide layer 20.
Nitride layer 24 can comprise, for example, silicon nitride, and is provided to further electrically insulate conductive layers 18 and 20 from other conductive layers which may ultimately be formed proximate layers 18 and 20. Nitride layer 24 is a thick layer (a typical thickness can be on the order of several hundred, or a few thousand Angstroms) and can create stress on underlying layers. Accordingly, another function of oxide layer 22 is to alleviate stress induced by nitride layer 24 on underlying layers 18 and 20.
Antireflective material layer 26 can comprise, for example, an organic layer that is spun over nitride layer 24. Alternatively, layer 26 can be a deposited inorganic antireflective material, such as, for example, SixOyNz:H, wherein x is from 0.39 to 0.65, y is from 0.02 to 0.56, and z is from 0.05 to 0.33. In practice the layer can be substantially inorganic, with the term “substantially inorganic” indicating that the layer can contain a small amount of carbon (less than 1% by weight). Alternatively, if, for example, organic precursors are utilized, the layer can have greater than or equal to 1% carbon, by weight.
Photoresist layer 28 can comprise either a positive or a negative photoresist. Photoresist layer 28 is patterned by exposing the layer to light through a masked light source. The mask contains clear and opaque features defining a pattern to be created in photoresist layer 28. Regions of photoresist layer 28 which are exposed to light are made either soluble or insoluble in a solvent. If the exposed regions are soluble, a positive image of the mask is produced in photoresist layer 28 and the resist is termed a positive photoresist. On the other hand, if the non-radiated regions are dissolved by the solvent, a negative image results, and the photoresist is referred to as a negative photoresist.
A difficulty that can occur when exposing photoresist layer 28 to radiation is that waves of the radiation can propagate through photoresist 28 to a layer beneath the photoresist and then be reflected back up through the photoresist to interact with other waves of the radiation which are propagating through the photoresist. The reflected waves can constructively and/or destructively interfere with the other waves to create periodic variations of light intensity within the photoresist. Such variations of light intensity can cause the photoresist to receive non-uniform doses of energy throughout its thickness. The non-uniform doses can decrease the accuracy and precision with which a masked pattern is transferred to the photoresist. Antireflective material 26 is provided to suppress waves from reflecting back into photoresist layer 28. Antireflective layer 26 comprises materials which absorb and/or attenuate radiation and which therefore reduce or eliminate reflection of the radiation.
FIG. 2 shows semiconductive wafer fragment 10 after photoresist layer 28 is patterned by exposure to light and solvent to remove portions of layer 28.
Referring to FIG. 3, a pattern from layer 28 is transferred to underlying layers 16, 18, 20, 22, 24, and 26 to form a patterned stack 30. Such transfer of a pattern from masking layer 28 can occur by a suitable etch, such as, for example, a plasma etch utilizing one or more of Cl, HBr, CF4, CH2F2, He, and NF3.
After the patterning of layers 16, 18, 20, 22, 24 and 26, layers 28 and 26 can be removed to leave a patterned gate stack comprising layers 16, 18, 20, 22, and 24.
A continuing goal in semiconductor wafer fabrication technologies is to reduce process complexity. Such reduction can comprise, for example, reducing a number of process steps, or reducing a number of layers utilized in forming a particular semiconductor structure. Accordingly, it would be desirable to develop alternative methods of forming patterned gate stacks wherein fewer steps and/or layers are utilized than those utilized in the prior art embodiment described with reference to FIGS. 1-3.